1. Field of the Invention
The present invention relates generally to a planar DMOS power transistor and its manufacturing method and, more particularly, to a self-aligned source structure of a planar DMOS power transistor and its manufacturing methods.
2. Description of the Prior Art
A DMOS power transistor with very low on-resistance has become an important device for applications in battery protection, switching, linear regulator, amplifier and power management. It is known that device ruggedness becomes a major reliability issue of the DMOS power transistor and the device ruggedness due to parasitic bipolar transistors formed between source, body and drain becomes a major concern. The parasitic bipolar transistors can be activated to cause a snap back effect which can result in permanent damages to the DMOS power transistor. Several methods had been proposed to improve the parasitic resistances of the parasitic bipolar transistors, however additional critical masking photoresist steps are in general required.
FIG. 1A shows a schematic cross-sectional view for a source structure of a prior art planar DMOS power transistor as disclosed in U.S. Pat. No. 5,268,586 by Mukherjee et al., in which a p-body diffusion region 50 is formed in an n− epitaxial silicon layer 40 on an n+ silicon substrate 30 through a first implantation window (not shown) surrounded by a patterned polycrystalline-silicon gate layer 80 on a gate oxide layer 70 using a first masking photoresist step; a heavily-doped n+ diffusion ring 60 is formed in a surface portion of the p-body diffusion region 50 through a second implantation window (not shown) formed between a patterned second masking photoresist layer (not shown) being formed on a central portion of the p-body diffusion region 50 and the patterned polycrystalline-silicon gate layer 80 on the gate oxide layer 70; a p+ diffusion region 140 is formed within the p-body diffusion region 50 by a high-energy ion implantation through the first implantation window surrounded by the patterned polycrystalline-silicon gate layer 80 on the gate oxide layer 70; a source contact window is formed by an opening through a silicon oxide layer 90 using a third masking photoresist step; and a contact metal layer 110 is formed on a portion of the heavily-doped n+ diffusion ring 60 and the p+ diffusion region 140 surrounded by the heavily-doped n+ diffusion ring 60.
Apparently, three masking photoresist steps are required to form the source structure shown in FIG. 1A, in which two critical masking photoresist steps (second and third masking photoresist steps) are required and non-uniform current distribution due to non-uniform n+ contact width and parasitic n+ diffusion ring resistance are inevitable. Moreover, it is clearly seen that the p+ diffusion region 140 formed by the high-energy ion implantation must have a peak doping concentration smaller than a tail doping concentration in the heavily-doped n+ diffusion ring 60 without increase the parasitic n+ diffusion ring resistance and contact resistance of the contact metal layer 110 on the p+ diffusion region 140 becomes larger due to a lower surface doping concentration of the p+ diffusion region 140. In addition, a poor metal step coverage or a larger parasitic capacitance between the contact metal layer 110 and the patterned polycrystalline-silicon gate layer 80 can be obtained.
FIG. 1B shows a schematic cross-sectional view for a source structure of another prior art planar DMOS power transistor as disclosed in U.S. Pat. No. 5,930,630 by Hshieh et al., in which a p-body diffusion region 130 is formed in an n− epitaxial silicon layer 110 on an n+ silicon substrate 105 through a first implantation window (not shown) surrounded by a patterned polycrystalline-silicon gate layer 125 on a gate oxide layer 120 using a first masking photoresist step; Similarly, a heavily-doped n+ diffusion ring 140 is formed through a second implantation window formed between a patterned second masking photoresist layer (not shown) being formed on a central portion of the p-body diffusion region 130 and the patterned polycrystalline-silicon gate layer 125 on the gate oxide layer 120 by using a second masking photoresist step; a third implantation window is formed through a BP-glass layer 145 over a P-glass layer 148 on the gate oxide layer 120 by using a third masking photoresist step; a high-energy and a low-energy implantations are performed in sequence to form a deep p+ diffusion region 165 and a shallow p+ diffusion region 160; a shallow trench is performed on an exposed heavily-doped n+ diffusion ring 140 and the shallow p+ diffusion region 160 through the third implantation window; and a contact metal layer 170 is formed on the shallow trench and over a reflow BP-glass layer 145 over the P-glass layer 148 on the gate oxide layer 120.
Apparently, three masking photoresist steps are required to form FIG. 1B, in which two critical masking photoresist steps (second and third masking photoresist steps) are also required, as those described in FIG. 1A. It is clearly seen that the shallow trench used to reveal the peak doping concentration portion of the shallow p+ diffusion region 160 may simultaneously remove the peak doping concentration portion of the heavily-doped n+ diffusion ring 140, resulting in an increase of the parasitic n+ diffusion ring resistance and the contact resistance between the contact metal layer 170 and the trenched n+ diffusion ring 140. It should be emphasized that the doping concentration of the shallow p+ diffusion region 160 in FIG. 1B must keep to be smaller than the doping concentration in the heavily-doped n+ diffusion ring 140, therefore the shallow trench doesn't improve an overall contact resistance of the heavily-doped n+ source diffusion ring 140 and the p-body diffusion region 130.
From FIG. 1A and FIG. 1B, it is clearly seen that three masking photoresist steps are required to form the source structure, in which two critical masking photoresist steps may produce non-uniform heavily-doped n+ diffusion ring and non-uniform contact width between the heavily-doped n+ diffusion ring and the contact metal layer and the contact resistance between the p+ diffusion region and the contact metal layer is higher due to a lower surface doping concentration in the p+ diffusion region. Apparently, non-uniform current flow may occur for either DMOS power transistor cell or parasitic npn and pnp bipolar transistors due to misalignments of the critical masking photoresist steps, especially as source area of a DMOS power transistor cell is reduced. Moreover, an additional high-energy implantation is required and the cost of production is increased.
It is therefore a major objective of the present invention to offer a fully self-aligned source structure for a planar DMOS power transistor in order to eliminate all detrimental effects due to misalignments of the critical masking photoresist steps.
It is another objective of the present invention to offer a fully self-aligned source structure being fabricated by using only one masking photoresist step.
It is a further objective of the present invention to offer a scalable self-aligned source structure with a minimized cell size.